//寄存器堆
module registers(clk, reset, readRegister1, readRegister2, writeRegister, writeData,
                    readData1, readData2, regWrite);
    input wire[4:0] readRegister1, readRegister2, writeRegister; //要读/写的寄存器
    input wire regWrite; //寄存器写信号
    input wire clk, reset;
    input wire[31:0] writeData;  //写寄存器数据

    output reg[31:0] readData1, readData2; //读寄存器数据

    reg[31:0] regs[31:0]; //寄存器堆

    always @(posedge reset)
    begin
        regs[0] <= 32'h0000;
        regs[1] <= 32'h0000;
        regs[2] <= 32'h0000;
        regs[3] <= 32'h0000;
        regs[4] <= 32'h0000;
        regs[5] <= 32'h0000;
        regs[6] <= 32'h0000;
        regs[7] <= 32'h0000;
        regs[8] <= 32'h0000;
        regs[9] <= 32'h0000;
        regs[10] <= 32'h0000;
        regs[11] <= 32'h0000;
        regs[12] <= 32'h0000;
        regs[13] <= 32'h0000;
        regs[14] <= 32'h0000;
        regs[15] <= 32'h0000;
        regs[16] <= 32'h0000;
        regs[17] <= 32'h0000;
        regs[18] <= 32'h0000;
        regs[19] <= 32'h0000;
        regs[20] <= 32'h0000;
        regs[21] <= 32'h0000;
        regs[22] <= 32'h0000;
        regs[23] <= 32'h0000;
        regs[24] <= 32'h0000;
        regs[25] <= 32'h0000;
        regs[26] <= 32'h0000;
        regs[27] <= 32'h0000;
        regs[28] <= 32'h0000;
        regs[29] <= 32'h0000;
        regs[30] <= 32'h0000;
        regs[31] <= 32'h0000;
    end

    always @(readRegister1, readRegister2, writeRegister, regWrite, writeData)
    begin
        readData1 <= regs[readRegister1];

        readData2 <= regs[readRegister2];

        if(regWrite)
        begin
            regs[writeRegister] <= writeData;
        end
         
    end

endmodule